This invention relates generally to analogue-to-digital converters (ADCs) and in particular to successive approximation analogue-to-digital converters, and is more particularly directed toward a successive approximation analogue-to-digital converter that uses continuous error correction to allow the individual bit trials to take place in a much shorter time period than that required for a conventional successive approximation ADC.
Successive approximation ADC is the name commonly given to an analogue-to-digital conversion process in which digital approximations of the input analogue voltage are determined on the basis of a binary search. A digital value stored in an n-bit successive approximation register (SAR) is input to a digital-to-analogue converter, and a decision is made as to whether the value in the SAR represents an analogue voltage that is higher or lower than the input analogue value.
The initial value of the SAR is conventionally set to one-half the number that can be represented in the n bits of the SAR. To be more precise, an n-bit register can contain a value of 2nxe2x88x921, but for purposes of successive approximation, the initial value has the most significant bit set and the others cleared, which translates into a value of 2n/2. If this comparison reveals that the digital approximation is indeed lower than the input voltage, the bit that was initially set remains set, the bit of next greater significance is also set, and another trial commences. If on the other hand, the SAR value is greater than the input analogue voltage, the bit that was set for that trial is cleared, the bit of next greater significance is set, and another trial commences. It can be appreciated from this example why a successive approximation approach bears such a similarity to a binary search procedure.
Each bit of the SAR is set or cleared based upon a trial, so the conversion process requires only xe2x80x9cnxe2x80x9d trials to reach completion. SAR-type algorithms achieve conversion in much less time than a ramp-up technique. A ramp-up type of conversion, for example, requires that the input register of the D/A converter xe2x80x9ccount-upxe2x80x9d by increments of 1 until the analogue value is reached. Since each increment of the input register requires a trial to determine whether the analogue input level has been reached, many trials may have to be performed before a successful conversion is achieved. There are other types of conversion systems that are even faster than SAR ADC, such as pipeline, flash, and half-flash, but these techniques require much more power than the SAR approach, and are thus unsuitable in many applications.
The main difficulty in A/D conversion generally is settling time. The digital value that is written to the input register (the SAR register in a successive approximation system) produces an analogue output at the D/A converter which must be allowed to settle completely before a comparison is performed in order to guarantee system accuracy.
Since the practice of limiting settling times in order to speed up conversion can lead to errors, the addition of an algorithm that can correct at least some mistakes is an important improvement.
Accordingly, a need arises for a successive approximation ADC that affords the opportunity to correct errors while still operating at a higher speed than conventional SAR ADCs. The successive approximation ADC should provide enhanced capabilities without undue added complexity, cost, or power consumption.
These shortcomings of the prior art, and others, are addressed by the successive approximation ADC of the present invention. As the name suggests, an error correcting SA-ADC allows correction, later in the conversion, of errors made during prior bit-trial comparisons, provided the errors are below a certain size. The ability to correct for errors later on requires the total code correction achievable during subsequent bit trials to be greater than the code change due to the bit-weight at the location of the error, plus the error that exists to cause the incorrect decision.
The penalty for being able to correct for errors is an increased amount of digital circuitry and more comparator decisions to allow for redundancy. The increased digital circuitry is not generally a problem on today""s fine-line technologies, although higher digital cross-talk and noise levels will be apparent in a tightly-packed, complex geometry. The algorithm of the invention typically requires about a 30 to 40 percent increase in the number of trials performed, but the increase could be 200 percent or more under certain circumstances. Of course, these additional trials may be performed at a very much faster rate with the inventive algorithm. Another advantage of the algorithm of the invention is that increasing the resolution of the converter does not require each bit trial to have a longer settling time, only more bit trials.
In accordance with one embodiment of the invention, an improved successive approximation analogue-to-digital converter system is provided. The system includes a D/A converter and a comparison capability, wherein a first trial value is stored in a successive approximation register and a comparison is made of relative amplitude of D/A converter output with respect to analogue signal amplitude, and an iterative process is performed in which a subsequent trial value is stored in the successive approximation register before the comparison is repeated. The improvement comprises conducting only one comparison for each trial, with the subsequent trial value for a plurality of iterations being greater than one-half the first trial value, such that a first trial value determined in error is corrected during subsequent iterations.
For at least one iteration, the subsequent trial value is equal to one-half the first trial value, and, for at least one iteration, the subsequent trial value is equal to the first trial value. The subsequent trial value may be obtained from a table of subsequent trial values, and the table may be so arranged that each subsequent trial value entry is stored with an associated iteration number. In one form of the invention, the subsequent trial value is approximately 62% of the first trial value.
In accordance with another aspect of the invention, an analogue-to-digital conversion system is provided that includes a D/A converter and a comparison capability, and a successive approximation register to which a code value is written, the successive approximation register coupled to an input of the digital-to-analogue converter. A method is provided for determining a digital representation of an analogue input signal, the method comprising the steps of storing an initial code value in the successive approximation register to provide a stored code value, waiting a predetermined time interval for the digital-to-analogue converter output to settle in response to the stored code value, and comparing the analogue input signal to the digital-to-analogue converter output to provide a comparison indication. The stored code value is corrected in accordance with the comparison indication, and the process is repeated until a predetermined number of trials have been completed. The next trial weight value is greater than one-half the stored code value, such that a stored code value determined in error is corrected during subsequent trials. The step of correcting the stored code value may comprise adding a next trial weight to the stored code value, or it may comprise subtracting a next trial weight from the stored code value.
In accordance with still another aspect of the invention, the step of storing an initial code value in the successive approximation register further comprises the steps of retrieving a predetermined initial code value from a memory storage location, and storing the predetermined initial code value in the successive approximation register.
In one form of the invention, the step of storing an initial code value in the successive approximation register further comprises the steps of computing an initial code value based, at least in part, upon number of bits in the successive approximation register, and storing the computed initial code value in the successive approximation register. In one form of the invention, the first code value is equal to 2nxe2x88x921, where n is the number of bits in the successive approximation register.
In yet another aspect of the invention, an integer value corresponding to current trial number is stored in a memory storage location, and the step of waiting a predetermined time interval comprises determining the time interval based, at least in part, upon the current trial number. The step of correcting the stored code value may further include the steps of retrieving a next trial weight value from a table stored in memory, and adding the next trial weight value to the stored code value or subtracting the next trial weight value from the stored code value. Preferably, the next trial weight value is stored in the memory table in association with the current trial number.
In still another form of the invention, the step of correcting the stored code value further comprises the steps of computing the next trial weight based upon the stored code value, and either adding the computed next trial weight value to the stored code value or subtracting the next trial weight value from the stored code value.
In another aspect of the present invention, an analogue-to-digital converter comprises digital-to-analogue converter means, successive approximation register means coupled to the input of the digital-to-analogue converter means, means for storing an initial code value in the successive approximation register means to provide a stored code value, means for waiting a predetermined time interval for the digital-to-analogue converter means output to settle in response to the stored code value, means for comparing an analogue input signal to the digital-to-analogue converter means output to provide a comparison indication, and means for correcting the stored code value in accordance with the comparison indication, wherein only a single comparison is made for each trial, and the next trial weight value is greater than one-half the stored code value, such that a stored code value determined in error is corrected during subsequent trials.
In one form of the invention, the means for correcting the stored code value comprises means for adding the next trial weight value to the stored code value, or means for subtracting the next trial weight value from the stored code value.
In accordance with another form of the invention, the means for storing an initial code value in the successive approximation register means further comprises means for retrieving a predetermined initial code value from a memory means, and means for storing the predetermined initial code value in the successive approximation register means.
The means for storing an initial code value in the successive approximation register means may further comprise means for computing an initial code value based, at least in part, upon number of bits in the successive approximation register means, and means for storing the computed initial code value in the successive approximation register means. In one form of the invention, the first code value is equal to 2nxe2x88x921, where n is the number of bits in the successive approximation register means.
In another form of the invention, an integer value corresponding to current trial number is stored in a memory means, and the means for waiting a predetermined time interval comprises determining the time interval based, at least in part, upon the current trial number. The means for correcting the stored code value may comprise means for retrieving a next trial weight value from a table stored in the memory means, and means for adding the next trial weight value to the stored code value, or means for subtracting the next trial weight value from the stored code value. Preferably, the next trial weight value is stored in a memory table in association with the current trial number.
In still a further aspect of the invention, the means for correcting the stored code value further comprises means for computing the next trial weight based upon the stored code value, and means for adding the computed next trial weight value to the stored code value, or means for subtracting the next trial weight value from the stored code value.
Further objects, features, and advantages of the present invention will become apparent from the following description and drawings.